HW#5 LNA Optimization and PLL Design

1, 2 任選一題

3,4 任選一題

1. Make a GD/(A*)+MNA Optimizer on a Apple C1 LNA Die

Hint: artifact, share

DE+MNA Optimizer on Die artifact

2. To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.

Must verify your results to meet spec and parameters have to be realistic.

Hint: (DE+MNA Optimizer on Die artifact) 

3. (a) Build a 9.0 GHz 65 nm Fractional-N PLL Synthesizer with NM Optimization 

(b)  Cross check your PLL  by MNA

Hint: What is NM method? NM Algo

4.

(a) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7

Apple C1 ADPLL — 7.0 GHz  

(b) Cross check your Apple C1 ADPLL  by MNA