2026年3月27日 星期五

HW#5 LNA Optimization and PLL Design

1, 2 任選一題

3,4 任選一題


1. Make a GD/(A*)+MNA Optimizer on a Apple C1 LNA Die

Hint: artifactshare


DE+MNA Optimizer on Die artifact


2. To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.
Must verify your results to meet spec and parameters have to be realistic.

Hint: (DE+MNA Optimizer on Die artifact



3. (a) Build a 9.0 GHz 65 nm Fractional-N PLL Synthesizer with NM Optimization 


Hint: What is NM method? NM Algo


4.

(a) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7

Apple C1 ADPLL — 7.0 GHz  





EX#5

   Handouts


Comparison of LLMs
Claude Opus 4.6 optimal (visualizing how AI thinks)
Gemini 3.0 Pro 推理,optimal
ChatGPT 5, end results 流程圖  feasible, not optimal,

  課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject EX#5 [your id, your name]

1,2 任選1

3,4 任選1


1. 
Design a Two-Stage BJT Amplifier according to goals specified using A* (Parameters to optimize RE1, RC1. RE2. RC2) 




2. Optimize LM3886 class AB audio amplifier IC using A* (Parameters to optimize: resistors except the load) 



the architecture inside the LM3886 and TDA7293
optimizer A* (share)


3. 搶救感恩節晚餐大作戰講義 題目 使用AI推理或用程式計算出最佳計畫, 然後將求解過程視覺化


推理視覺化(動畫)

style 1


style 2



A* 搜尋樹狀圖(動畫)

style 1


style 2



4. 搶救感恩節晚餐大作戰講義 題目 使用AI推理或用程式計算出最佳計畫, 然後將得出結果視覺化



狀態圖(State Diagram) 









state diagram with aligned timeline





看板圖 (Kanban)


 (interactive timeline)




流程圖(Flow chart)




timed flowchart with interactive timeline (share)




2026年3月17日 星期二

HW#4 RF IC Design

  

建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換,免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)



How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link


Content share 作業繳交格式

  • share only link, pure text, markdown (md)
  • no attachments accepted, no html, screen dump, or png
  • non-compliant homework will be rejected and returned to you


課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#4  [your id, your name]


3/10 只要做第一題(內有5小題)


Study Apple C1 Architecture

1. (a) On Claude, Run NGSpice for the LNA using given parameters. If the results do not match, explain why.

(b) Run an MNA simulation (Modified Nodal Analysis, as used in Cadence Spectre engine)

 

Optimized parameters (share)


MNA simulation


(c)  Perform DRC (Design Rule Check) for the  3.5 GHz LNA. If it is not entirely design rule compliant, redesign to make the layout more DRC driven.







(DRC, share) (DRC-driven, artifact)




2. (a) Run the Simplified LNA optimizer on Die, 3.5 GHz LNA TSMC N7. Use MNA (Modified Nodal Analysis, as used in Cadence Spectre engine)  to optimize again. Must verify your results to meet spec and parameters have to be realistic.

Hint: (GD/(A*)+MNA Optimizer on Die artifactshare)


DE+MNA Optimizer on Die artifact


(b) To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.
Must verify your results to meet spec and parameters have to be realistic.

Hint: (DE+MNA Optimizer on Die artifact


3. (a) Build a 9.0 GHz Fractional-N PLL Synthesizer: 9.0 GHz PLL with A* Optimization, (share) 65 nm
(b) Build a 9.0 GHz Fractional-N PLL Synthesizer with NM Optimization

(c) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7

Apple C1 ADPLL — 7.0 GHz  


(d) Build Apple C1 ADPLL with NM Optimization

Hint: What is NM method? NM Algo