HW#12 PnR for Apple C1 PLL and RISC Core CPU

  1. Build a model of Apple C1 ADPLL — 7.0 GHz (spec) with A* and NM Version, NM cross checked by MNA,  

2. Enhance the Apple C1 PLL model with DTC by building an Optimizer with MNA-powered trajectory. share, DTC-Solver

You may refer to schematic, architecture and timing, DTC-TDC Timing (share)

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)

Head-to-head

3. Macro Routing for a RISC core CPU

 baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

Bit sliced macro 28, metal layers 9, die 690 × 750 μm