建議工具
使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)
使用 ChatGPT 5 推理模式(自動切換)
使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)
使用 Grok 4 推理模式(自動切換)
How to publish a Claude artifact
Content share 作業繳交格式
- share only link, pure text, markdown (md)
- no attachments accepted, no html, screen dump, or png
- non-compliant homework will be rejected and returned to you
課堂練習
Deadline: This Saturday at 23:59
Send all the share links to me chang212@gmail.com by email with subject HW#4 [your id, your name]
3/10 只要做第一題（內有5小題）
Study Apple C1 Architecture
1. (a) On Claude, Run NGSpice for the LNA using given parameters. If the results do not match, explain why.
(b) Run an MNA simulation (Modified Nodal Analysis, as used in Cadence Spectre engine)
MNA simulation
(c) Perform DRC (Design Rule Check) for the 3.5 GHz LNA. If it is not entirely design rule compliant, redesign to make the layout more DRC driven.
2. (a) Run the Simplified LNA optimizer on Die, 3.5 GHz LNA TSMC N7. Use MNA (Modified Nodal Analysis, as used in Cadence Spectre engine) to optimize again. Must verify your results to meet spec and parameters have to be realistic.
DE+MNA Optimizer on Die artifact
(b) To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.
Must verify your results to meet spec and parameters have to be realistic.
Hint: (DE+MNA Optimizer on Die artifact)
3. (a) Build a 9.0 GHz Fractional-N PLL Synthesizer: 9.0 GHz PLL with A* Optimization, (share) 65 nm
(c) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7
Apple C1 ADPLL — 7.0 GHz
(d) Build Apple C1 ADPLL with NM Optimization
Hint: What is NM method? NM Algo
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