HW#6 PLL

 本次習題基本說明

進階說明

 1. (a) Build a 9.0 GHz 65 nm Fractional-N PLL Synthesizer with NM Optimization 

(b)  Cross check your PLL  by MNA

Hint: What is NM method? NM Algo

2.

(a) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7

Apple C1 ADPLL — 7.0 GHz  

(b) Cross check your Apple C1 ADPLL  by MNA